The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a power transistor especially used to amplify ultra high frequencies, that is, a semiconductor device having a plurality of transistor units with a so-called multi-finger structure each of which is constituted by an interdigital electrode, and a unit prepared by arranging a plurality of unit cells each made up of a drain, gate, and source to be adjacent to each other, and a method of manufacturing the same.
Compact, lightweight devices with high efficiency are demanded for semiconductor devices for amplifying high-frequency signals of several hundred MHz or more, e.g., high-frequency power transistors used on the transmission stage of a portable telephone. Particularly, high-frequency power transistors used in a portable telephone using a battery as a power source must be reduced in power amplification circuit current and increased in amplification efficiency.
To meet these demands, there is proposed a power transistor having a multi-finger structure in which a plurality of unit cells each made up of a drain, gate, and source are arranged adjacent to each other, and the drain and gate are alternately connected to comb finger electrodes, thereby forming a field effect transistor (FET) (e.g., Japanese Utility Model Laid-Open No. 51-80063).
FIG. 19 shows the arrangement of an FET having a multi-finger structure with such comb finger electrodes.
Unit cells each made up of a drain, gate, and source are arranged adjacent to each other on the major surface of a semiconductor substrate. The gate and drain of each unit cell are respectively connected to comb-finger-shaped gate and drain finger electrodes 8 and 12.
The source of each unit cell is connected to a p+-implanted layer (not shown in FIG. 19) via a source contact 1d and an electrode 2 immediately above the source.
Each gate finger electrode 8 is connected to a gate extraction electrode 12b, and each drain finger electrode 12 is connected to a drain extraction electrode 12a. The gate and drain extraction electrodes 12b and 12a are respectively connected to gate and drain pads 22 and 21 for connecting bonding wires.
An FET constituted by a plurality of unit cells arranged adjacent to each other, the comb finger gate electrode (the gate finger electrodes 8 and gate extraction electrode 12b), and the comb finger drain electrode (the drain finger electrodes 12 and drain extraction electrode 12a) is called a transistor unit 30.
To obtain a large output from a power transistor, the finger length and the number of finger electrodes are increased in a power transistor having this multi-finger structure, thereby increasing the gate width of the whole element.
However, a long gate finger increases the gate resistance and degrades high-frequency characteristics. If the number of finger electrodes is increased, the chip becomes elongated, and high-frequency characteristics are degraded by a phase shift between finger electrodes.
To solve these problems, a semiconductor device having the conventional multi-finger structure achieves a high output by arranging a plurality of transistor units and increasing the gate width. At the same time, the area efficiency is increased by laying out the gate and drain pads of respective transistor units close to each other.
There is further provided a semiconductor device having a so-called fishbone structure in which a pair of transistor units share a gate extraction electrode to increase the degree of integration.
FIG. 20 shows an example of the arrangement of a power transistor having such a fishbone structure.
A pair of transistor units are constituted by a gate extraction electrode 12b which extends between a pair of two units each prepared by arranging a plurality of unit cells each made up of a drain, gate, and source adjacent to each other, and which is commonly connected to gate finger electrodes 8 of respective unit cells, and two drain extraction electrodes 12a each of which extends to a position where the drain extraction electrode 12a faces the gate extraction electrode 12b and a corresponding unit, and which is commonly connected to drain finger electrodes 12 of the unit.
This structure is called a fishbone structure from the shape of the gate extraction electrode 12b commonly connected to the gate finger electrodes 8.
Note that the fishbone structure also includes a structure having one drain extraction electrode and two gate extraction electrodes, in addition to the above structure having one gate extraction electrode and two drain extraction electrodes. In other words, a structure having a drain extraction electrode which extends between a pair of units and is commonly connected to drain finger electrodes of respective unit cells, and two gate extraction electrodes each of which extends to a position where the gate extraction electrode faces the drain extraction electrode and a corresponding unit, and is commonly connected to gate finger electrodes 8 of the unit is also called a fishbone structure.
One end of the gate extraction electrode 12b is connected to a gate pad 22 for connecting a boding wire. The two drain extraction electrodes 12a are commonly connected to one drain pad 21 at an end opposite to the gate pad 22.
This structure in which two transistor units share the gate extraction electrode 12b and the two drain extraction electrodes 12a are commonly connected to one drain pad 21 is called a transistor unit pair or fishbone cell.
The power transistor in this example is constituted by arranging parallel a plurality (four in FIG. 20) of transistor unit pairs which share a gate extraction electrode.
The power transistor may be constituted by arranging parallel a plurality of transistor unit pairs (fishbone cells) each having one drain extraction electrode and two gate extraction electrodes.
To prevent oscillation and stabilize operation in a conventional semiconductor device having a plurality of transistor unit pairs, adjacent gate pads 22 are connected by gate extraction electrode connection wiring lines 23 made of a conductor such as Al, and adjacent drain pads 21 are connected by drain extraction electrode connection wiring lines 24, as shown in FIG. 20.
However, oscillation cannot always be prevented even if a plurality of transistor unit pairs (or transistor units) are connected by conductors. In particular, the semiconductor device tends to oscillate with a large number of transistor unit pairs (or transistor units) and a large total gate width.
For example, FIG. 21 shows a graph of static characteristics of the drain current in the semiconductor device formed on an Si substrate with the arrangement shown in FIG. 20 when the gate width is 40 mm, and gate or drain pads are connected to each other. In FIG. 21, the abscissa and ordinate respectively represent the drain voltage and drain current using the gate voltage as a parameter. Although the drain current increases together with the gate voltage, the semiconductor device oscillates to distort the drain voltage vs. drain current graph.
The semiconductor device made up of a plurality of transistor unit pairs (or transistor units) oscillates because operation states are different between respective transistor unit pairs (or transistor units) even within a single chip, and this unbalance increases phase interference between the transistor unit pairs (or transistor units). Oscillation arising from this phase interference is called loop oscillation.
In the conventional semiconductor device, even if gate or drain pads are connected to each other, and one of the pads fails to be connected by a bonding wire, this error of the semiconductor device cannot be detected by DC screening. To detect a bonding error critically influencing a high-frequency operation of the semiconductor device, time-consuming, high-cost, radio frequency (RF) screening must be conducted.
The present invention has been made in consideration of these problems, and has as its object to prevent oscillation of a semiconductor device constituted by a plurality of transistor units or transistor unit pairs.
It is another object of the present invention to provide a semiconductor device in which gate pads or drain pads are connected to each other, and a bonding error can be detected by DC screening without any RF screening, and a method of manufacturing the same.
To achieve the above objects, according to the present invention, there is provided a semiconductor device having a plurality of transistor units or transistor unit pairs, wherein gate pads of adjacent transistor units are connected to each other by a gate extraction electrode connection wiring line having a resistor of 0.6 to 10 xcexa9, and drain pads are connected to each other by a drain extraction electrode connection wiring line.
The transistor unit is constituted by a unit prepared by arranging a plurality of unit cells each made up of a drain, gate, and source adjacent to each other on the major surface of a semiconductor substrate, a gate extraction electrode which extends in a direction perpendicular to the longitudinal direction of the gate and is commonly connected to the gates of the unit cells, a drain extraction electrode which is positioned at a side where the drain extraction electrode faces the gate extraction electrode via the unit, extends in a direction perpendicular to the longitudinal direction of the drain, and is commonly connected to the drains of the unit cells, a gate pad connected to the gate extraction electrode, and a drain pad connected to the drain extraction electrodes.
As described above, the transistor unit pair means a pair of parallel transistor units which share the gate or drain extraction electrode.
In other words, the transistor unit pair is constituted by a pair of units each prepared by arranging a plurality of unit cells each made up of a drain, gate, and source adjacent to each other on the major surface of a semiconductor substrate, a gate extraction electrode which extends between the pair of units in a direction perpendicular to the longitudinal direction of the gate and is commonly connected to the gates of the unit cells of these units, two drain extraction electrodes which are positioned at sides where the drain extraction electrodes respectively face the gate extraction electrode via the pair of units, extend in a direction perpendicular to the longitudinal direction of the drain, and are commonly connected to the drains of the unit cells of corresponding units, a gate pad connected to one end of the gate extraction electrode, and a drain pad commonly connected to one end of each of the drain extraction electrodes that opposes the gate pad.
In the present invention, the transistor unit pair may comprise two gate extraction electrodes and a common drain extraction electrode.
The gate extraction electrode connection wiring line connects adjacent gate pads to electrically connect the gate extraction electrodes of adjacent transistor units or transistor unit pairs.
Similarly, the drain extraction electrode connection wiring line connects adjacent drain pads to electrically connect the drain extraction electrodes of adjacent transistor units or transistor unit pairs.
In the semiconductor device according to the present invention, loop oscillation caused by operational unbalance between transistor units or transistor unit pairs attenuates while passing through the resistor of the gate extraction electrode connection wiring line. In the present invention, gate pads are connected to each other by the gate extraction electrode connection wiring line having a resistor, thereby cutting off the loop oscillation and preventing oscillation of the semiconductor device such as a power transistor having a plurality of transistor units or transistor unit pairs.
In the present invention, gate pads are connected to each other via a resistor because the resistor does not depend on any frequency.
When the gate width is 40 mm or less, the resistance value of the gate extraction electrode connection wiring line is properly set to 0.6 to 10 xcexa9 depending on the total gate width of the semiconductor device, i.e., unit cells. The resistance value is set to 0.6 xcexa9 or more because loop oscillation cannot be attenuated and cut off at a resistance value less than 0.6 xcexa9, and the same problem arises as in the case in which gate pads are connected by a conductor (almost 0 xcexa9 in resistance). The resistance value is set to 10 xcexa9 or less because, especially in high-frequency operation, a resistance higher than 10 xcexa9 exhibits the same effects as in the case in which no gate pads are connected to each other, and makes operation unstable to allow the semiconductor device to oscillate, as in the case in which no gate pads are connected to each other.
In general, a proper resistance value of the gate extraction electrode connection wiring line has a relationship with the gain of the semiconductor device, more particularly, a total gate width Wg. The resistance value is empirically found to decrease as the total gate width Wg increases.
The present invention does not limit a combination of the total gate width Wg and the resistance value as far as the resistance value of the gate extraction electrode connection wiring line is 0.6 to 10 xcexa9 when the gate width is 40 mm or less. When the semiconductor substrate is made of Si and the total gate width (Wg) of unit cells is 40 mm or less, the resistance of the gate extraction electrode connection wiring line may be set to 1 to 8 xcexa9.
Transconductance (gm) can be attained by increasing the total gate width of the semiconductor device, whereas oscillation can be prevented.
In the present invention, the material and structure of the gate extraction electrode connection wiring line are not limited so long as the wire has the above-mentioned resistance value. The gate extraction electrode connection wiring line is characterized by being formed from a multilayered interconnection made of tungsten silicide (WSi) and polysilicon (poly-Si).
Of the materials used for semiconductor devices, WSi and undoped poly-Si are materials having relatively high resistivities. A WSi/poly-Si resistance can be used for part or all of the gate extraction electrode connection wiring line to realize a desired resistance value.
WSi can be used for the gate electrode to facilitate the semiconductor device manufacturing process.
In the present invention, drain pads are also connected to each other. In this case, the drain extraction electrode connection wiring line for connecting drain pads may be formed from a conductor almost 0 xcexa9 in resistance or may have a resistor. That is, the drain extraction electrode connection wiring line is formed from a conductor or a resistor less than 10 xcexa9.
The present invention can prevent oscillation with the resistor of the gate extraction electrode connection wiring line when the gain of the semiconductor device is large, e.g., when the total gate width Wg of the semiconductor is large or when the substrate is made of GaAs.
The present invention does not limit a combination of the total gate width Wg and the resistance value as long as the resistance value of the gate extraction electrode connection wiring line is set to 0.6 to 2.0 xcexa9, and the resistance value of the drain extraction electrode connection wiring line is set to 0.6 to 2.0 xcexa9 when the gate width is 78 mm or less.
Each of the gate and drain pads is formed from a first region connected to a gate or drain extraction electrode, a second region connected to the gate or drain extraction electrode connection wiring line, and a slit for insulating the first and second regions. The first and second regions may be connected to each other by a bonding wire.
Since the slits are formed in the gate and drain pads, when no bonding wire is connected to the gate or drain pad, the gate or drain of the transistor unit (or transistor unit pair) having this pad is electrically insulated from other transistor units (or other transistor unit pairs).
A bonding wire connection error can therefore be detected by measuring the drain current by DC screening without any RF screening using high frequencies.
In the present invention, the slits must be formed to electrically connect the first and second regions by a bonding wire, but the shape of the slits is not particularly limited. The first and second regions may be formed into a comb tooth shape via a slit. With this structure, the slit is formed into a zigzag shape to further ensure electrical connection between the first and second regions by a bonding wire.
The drain extraction electrode connection wiring line may comprise a fuse. In this structure, when each drain pad is connected by a lead serving as an external terminal of the semiconductor device and a bonding wire, almost no current flows through the drain extraction electrode connection wiring line in normal operation.
When, however, the bonding wire is disconnected between the drain pad and lead, the drain current flows into an adjacent drain pad via the drain extraction electrode connection wiring line to disconnect the fuse. As a result, the transistor unit (or transistor unit pair) connected to the disconnected bonding wire is electrically insulated from other transistor units (or other transistor unit pairs). An error of the bonding wire connected to the drain pad can be detected by measuring the drain current of the semiconductor device in DC screening.
Either one or both of the drain and gate pads may be connected to diodes.
Two or one end of the gate extraction electrode may be connected to a resistor of 1 to 16 xcexa9. This can prevent oscillation and attenuate the gain.
Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming in advance an underlying wafer in which a plurality of units are formed on the major surface of a semiconductor substrate, and appropriately changing a wiring layout of an uppermost layer of the underlying wafer to form a gate extraction electrode, a drain extraction electrode, a gate pad, and a drain pad into desired shapes, thereby manufacturing transistor units having a desired arrangement. According to this method, a MOSFET complying with a desired standard can be quickly manufactured in accordance with customer""s requirements.